1. Field of the Invention
The present invention relates to a manufacturing process for a chip package structure. More particularly, the present invention relates to a manufacturing process for a chip package structure having small thickness.
2. Description of Related Art
In the industry of the semiconductor, the production of integrated circuits (IC) can be mainly divided into three stages: IC design, IC fabrication process and IC package.
During the IC fabrication process, a chip is fabricated by the steps such as wafer process, IC formation and wafer sawing. A wafer has an active surface, which generally means the surface that a plurality of active devices is formed thereon. After the IC within the wafer is completed, a plurality of bonding pads are further formed on the active surface of the wafer so that the chip formed by wafer sawing can be electrically connected to a carrier through the bonding pads. The carrier may be a lead frame or a circuit board. The chip can be electrically connected to the carrier by wire bonding or flip chip bonding, so that the bonding pads on the chip are electrically connected to connecting pads of the carrier, thereby forming a chip package structure.
In general, in the manufacturing method of the conventional circuit board, a core dielectric layer is necessarily required, the patterned circuit layer and the patterned dielectric layer are inter-stacked on the core dielectric layer in a fully additive process, semi-additive process, subtractive process or other suitable process. Accordingly, the core dielectric layer may take a major proportion in the entire thickness of the circuit board. Therefore, if the thickness of the core dielectric layer can not be reduced effectively, it would be a big obstacle in reducing the thicknesses of the chip package.